AS3422 EK-ST

D a tas hee t A S3 4 2 1 A S 3 4 22 L o w P o w e r A m b ie n t No is e- C an ce ll in g S p e a k er Dr i ve r 1 General Description Line Input The AS3421/22 are speaker driver with Ambient Noise Cancelling function for headsets, headphones or ear pieces. It is intended to improve quality of e.g. music listening, a phone conversation etc. by reducing background ambient noise. An internal OTP-ROM can be optionally used to store the microphone gain calibration settings as well as all application specific settings. The AS3421/22 can be used in different configurations for best trade-off of noise cancellation, required filtering functions and mechanical designs.
64 steps @ 0.75dB and MUTE, pop-free gain setting
Fully differential stereo line inputs
Feed-forward cancellation
Feed-back cancellation with filter loop transfer function definable via simple RC components
Simple in production SW calibration
12-30dB noise reduction (headset dependent)
10-3000Hz wide frequency active noise attenuation (headset dependent) Monitor Function The simpler feed-forward topology is used to effectively reduce frequencies typically up to 2-3kHz. The feed-back topology with either 1 or 2 filtering stages has it strengths especially at very low frequencies. The typical bandwidth for feedback system is from 20Hz up to 1kHz which is a little bit lower than with feed forward systems. The filter loop for both systems is determined by measurements, for each specific headset individually, and depends very much on mechanical designs. The gain and phase compensation filter network is implemented with cheap resistors and capacitors for lowest system costs. AS3421/22 features also an audio playback only mode which allows the user to easily switch between ANC on and off mode. In ANC off mode unused blocks are automatically switch off to guaranty lowest power consumption in each operating mode. Microphone Input Volume control via serial interface or push buttons ANC processing The fully analog implementation allows the lowest power consumption, lowest system BOM cost and most natural received voice enhancement otherwise difficult to achieve with DSP implementations. The device is designed to be easily applied to existing architectures. 2 Key Features

For assisted hearing, i.e. to monitor announcements
Fixed (OTP prog.) ambient sound amplification to compensate headphone passive attenuation Incremental Functions
ANC with or without music on the receiving path
Music Playback mode for lowest power consumption
OTP ROM for automatic trimming during production (4 times programmable) Performance Parameter
7mA @ 1.5V stereo ANC; =1.4V , TA=25ºC, unless otherwise specified. Table 14. 2-Wire Serial Parameter Symbol Parameter Condition Min Typ Max Unit VCSL CSCL, CSDA Low Input Level (max 30%VBAT) 0 - 0.42 V VCSH CSCL, CSDA High Input Level CSCL, CSDA (min 70%VBAT) 0.98 - HYST CSCL, CSDA Input Hysteresis 200 450 800 VOL CSDA Low Output Level - - 0.4 V Tsp Spike insensitivity 50 100 - ns TH Clock high time TL Clock low time at 3mA V mV max. 400kHz clock speed 500 ns ns max. 400kHz clock speed 500 TSU CSDA has to change Tsetup before rising edge of CSCL 250 - - ns THD No hold time needed for CSDA relative to rising edge of CSCL 0 - - ns TS CSDA H hold time relative to CSDA edge for start/stop/rep_start 200 - - ns TPD CSDA prop delay relative to low going edge of CSCL 50 ns 1. Serial interface operates down to VBAT = 1.0V but with 100kHz clock speed and degraded parameters. www.austriamicrosystems.com Revision 0.90 27 - 61 Addr Name b7 b6 b5 b4 b3 b2 b1 b0 Audio Registers 00-07h reserved MIC_MODE 08h MIC_L 09h MIC_R 0Ah LINE_IN 0Bh GP_OP_L 0Ch GP_OP_R 0Dh-0Fh 18h-1Fh reserved reserved 0: StereoSingleEnd 1: MonoDiff MIC_REG_ON Revision 0.90 System Register 20h SYSTEM 21h PWR_SET MICL_VOL Gain from MICL to QMICL or Mixer = MUTE, -11.25dB...+36dB; 127 steps of 0.375dB 0: use reg 30h & 31h 1: use reg 08h & 09h MICR_VOL Gain from MICR to QMICR or Mixer = MUTE, -11.25dB...+36dB; 127 steps of 0.375dB LIN_REG_ON LIN_GAIN_+3dB 0: MUTE; 0x01..0x3F: Gain from LINR/L to QLINR/L or Mixer = -46.5dB...+0dB; 63 steps of 0.75dB with LIN_GAIN_+3dB bit set to ‘0’ 0x01..0x3F: Gain from LINR/L to QLINR/L or Mixer = -43.5dB...+3dB; 63 steps of 0.75dB with LIN_GAIN_+3dB bit set to ‘1’ HP_MUX OP2L 0: MIC; 1: OP1; 2: OP2; 3: open 0: OP2L inverting mode; 0x1..0xF: OP2L non inverting mode gain = 0...10.5dB; 15 steps of 0.75dB OP_REG_ON HP_MODE OP2R 0: use reg 34h 1: use reg 0Bh & 0Ch 0: StereoSingleEnd 1: MonoDiff 0: OP2R inverting mode; 0x1..0xF: OP2R non inverting mode gain = 0...10.5dB; 15 steps of 0.75dB Design_Version 1001 PWR_REG_ON HP_ON 0: use reg 0x35 1: use reg 0x21h LOW_BAT 22h-2Fh reserved LIN_VOL 0: use reg 33h and VOL pin 0: 0dB max. Line Gain 1: use reg 0Ah 1: +3dB max. Line Gain PWRUP_ COMPLETE OP2L_ON OP1L_ON OP2R_ON OP1R_ON REG3F_ON MONITOR_ON CONT_PWRUP PWR_HOLD MIC_ON LIN_ON MICS_CP_ON MICS_ON AS3421 AS3422 Table 15. I2C Register Overview Datasheet - R e g i s t e r D e s c r i p t i o n www.austriamicrosystems.com 10 Register Description 28 - 61 Name b7 b6 b5 b4 b3 b2 b1 b0 Revision 0.90 10h ANC_L2 TEST_BIT_5 11h ANC_R2 ALT1_LOCK 12h ANC_L3 TEST_BIT_6 13h ANC_R3 ALT2_LOCK 14h ANC_L4 TEST_BIT_7 15h ANC_R4 ALT3_LOCK 16h MICS_CNTR 17h PWRUP 30h ANC_L 31h ANC_R 32h MIC_MON 33h AUDIO_SET SEQ_LOCK GP_OP 35h OTP_SYS 3Eh CONFIG_1 3Fh CONFIG_2 0: ~900ms; 0Eh: ~600ms DEL_ ANC_MUX LIN_AGC_OFF MIC_AGC_OFF MICL_VOL_OTP Gain from MICL to QMICL or Mixer = MUTE, -11.25dB...+36dB; 127 steps of 0.375dB MICR_VOL_OTP TEST_BIT_2 Gain from MICR to QMICR or Mixer =MUTE, -11.25dB...+36dB; 127 steps of 0.375dB MIC_MON_OTP MON_MODE Gain from MICl/R to QMICL/R or Mixer = MUTE, -5.625dB...+41.6dB; 0.375dB steps, if MON_MODE is set to 0 0: fixed volume 1: adj. volume Gain from MICl/R to QMICL/R or Mixer = MUTE, -5.625dB...+41.6dB; 0.375dB steps, adjustable by VOL pin if MON_MODE is set to 1 VOL_BUTTON_ LINE_GAIN_+3dB MIC_MODE_ HP_MODE_ LIN_MON_ATTEN NO_PB_MODE_OTP MODE_OTP OTP OTP OTP 0: no attenuation; 0: PB mode enabled TEST_BIT_1 1: PB mode disabled 34h MICL_VOL_OTP2 Gain from MICL to QMICL or Mixer = MUTE, -11.25dB...+36dB; 127 steps of 0.375dB MICR_VOL_OTP2 Gain from MICR to QMICR or Mixer = MUTE, -11.25dB...+36dB; 127 steps of 0.375dB MICL_VOL_OTP3 Gain from MICL to QMICL or Mixer = MUTE, -11.25dB...+36dB; 127 steps of 0.375dB MICR_VOL_OTP3 Gain from MICR to QMICR or Mixer = MUTE, -11.25dB...+36dB; 127 steps of 0.375dB MICL_VOL_OTP4 Gain from MICL to QMICL or Mixer = MUTE, -11.25dB...+36dB; 127 steps of 0.375dB MICR_VOL_OTP4 Gain from MICR to QMICR or Mixer = MUTE, -11.25dB...+36dB; 127 steps of 0.375dB LowBat + 100mV FAST_START 0: Volume Mode disabled 0: 0dB max. Line Gain 1: Volume Mode enabled 1: +3dB max. Line Gain 0: StereoSingleEnd 1: MonoDiff 0: StereoSingleEnd 1: MonoDiff HP_MUX_OTP OP2_OTP 0: MIC; 1: OP1; 2: OP2; 3: - 0: OP2 inverting mode; 0x1..0xF: OP2 non inverting mode gain = 0...10.5dB; 15 steps of 0.75dB MAIN_LOCK 0: write reg 30h.. 35h 1: lock reg 30h..35h TEST_BIT_3 1..6: LIN_VOL shift by -6dB...-36dB 7: MUTE MON_HP_MUX CP_MODE 0: MIC; 1: OP1; 2: OP2; 3: - 0: Low noise, low voltage 1: High output voltage; OP2_ON_OTP OP1_ON_OTP MICS_CP_OFF I2C_MODE EXTBURNCLK OTP_MODE TM34 BURNSW TM_REG34-35 TM_REG30-33 29 - 61 0: READ; 1: LOAD; 2: WRITE; 3: BURN AS3421 AS3422 Addr OTP Register Datasheet - R e g i s t e r D e s c r i p t i o n www.austriamicrosystems.com Table 15. I2C Register Overview AS3421 AS3422 Datasheet - R e g i s t e r D e s c r i p t i o n Table 16. MIC_L Register Name Base Default MIC_L 2-wire serial 00h Left Microphone Input Register Offset: 08h Configures the gain for the left microphone input and defines the microphone operation mode. This register is reset at POR. Bit Bit Name Default Access Bit Description 7 MIC_MODE 0 R/W Selects the microphone input mode 0: single ended stereo mode 1: mono differential mode 6:0 MICL_VOL 000 0000 R/W Volume settings for left microphone input, adjustable in 127 steps of 0.375dB 00 0000: MUTE 00 0001: -11.25 dB gain 00 0010: -10.875 dB gain .. 11 1110: 35.625 dB gain 11 1111: 36 dB gain Table 17. MIC_R Register Name Base Default MIC_R 2-wire serial 00h Right Microphone Input Register Offset: 09h Configures the gain for the right microphone input and enables register 08h & 09h. This register is reset at POR. Bit Bit Name Default Access 7 MIC_REG_ON 0 R/W Defines which registers are used for the microphone settings. 0: settings of register 30h and 31h are used 1: settings of register 08h and 09h are used 6:0 MICR_VOL 000 0000 R/W Volume settings for right microphone input, adjustable in 127 steps of 0.375dB 00 0000: MUTE 00 0001: -11.25B gain 00 0010: -10.875 dB gain .. 11 1110: 35.625 dB gain 11 1111: 36 dB gain www.austriamicrosystems.com Bit Description Revision 0.90 30 - 61 AS3421 AS3422 Datasheet - R e g i s t e r D e s c r i p t i o n Table 18. LINE_IN Register Name Base Default LINE_IN 2-wire serial 00h Line Input Register Offset: 0Ah Configures the attenuation for the line input, defines the line input operation mode and enables register 0Ah. This register is reset at POR. Bit Bit Name Default Access Bit Description 7 LIN_REG_ON 0 R/W Defines which source is used for the line input settings. 0: settings of register 33h and VOL pin are used 1: register 0Ah is used 6 LINE_GAIN_+3dB 0 R/W Selects the line input operating gain range. If this bit is set the gain range of the line input amplifiers is shifted by +3dB. 0: Line Input gain range from -46.5dB...0dB 1: Line Input gain range from -43.5dB...+3dB 5:0 LIN_VOL 00 0000 R/W Volume settings for line input, adjustable in 63 steps of 0.75dB. the following gain settings are valid if LINE_GAIN_+3dB bit is set to ‘0’. 00 0000: MUTE 00 0001:-46.5dB gain 00 0010:-45.75dB gain .. 11 1110:-0.75dB gain 11 1111:.0 dB gain Volume settings for line input, adjustable in 63 steps of 0.75dB. the following gain settings are valid if LINE_GAIN_+3dB bit is set to ‘1’. 00 0000: MUTE 00 0001:-43.5dB gain 00 0010:-42.75dB gain .. 11 1110:+2.25dB gain 11 1111:+3 dB gain Table 19. GP_OP_L Register Name Base Default GP_OP_L 2-wire serial 00h Left General Purpose Operational Amplifier Register Offset: 0Bh Enables the left opamp stages, defines opamp 2 mode and gain and sets the HP input multiplexer. This register is reset at POR. Bit Bit Name Default Access 7:6 HP_MUX 00 R/W Multiplexes the analog audio signal to HP amp 00: MIC: selects QMICL/R output 01: OP1: selects QOP1L/R outputs 10:OP2: selects QOP2L/R output 11: open: no signal mixed together with the line input signal 5:2 OP2L 0000 R/W Mode and volume settings for left OP2, adjustable in 15 steps of 0.75dB 0000: OP2L in inverting mode 0001: 0 dB gain, OP2L in non inverting mode 0001: 0.75 dB gain, non inverting .., 1110: 9.75dB gain, non inverting 1111:.10.5 dB gain, non inverting www.austriamicrosystems.com Bit Description Revision 0.90 31 - 61 AS3421 AS3422 Datasheet - R e g i s t e r D e s c r i p t i o n Table 19. GP_OP_L Register Name GP_OP_L Base Default 2-wire serial 00h Left General Purpose Operational Amplifier Register Offset: 0Bh Enables the left opamp stages, defines opamp 2 mode and gain and sets the HP input multiplexer. This register is reset at POR. Bit Bit Name Default Access Bit Description 1 OP2L_ON 0 R/W Enables left OP 2 0: left OP2 is switched off 1: left OP2 is enabled 0 OP1L_ON 0 R/W Enables left OP 1 0: left OP1 is switched off 1: left OP1 is enabled Table 20. GP_OP_R Register Name GP_OP_R Base Default 2-wire serial 00h Right General Purpose Operational Amplifier Register Offset: 0Ch Enables the right opamp stages, defines opamp 2 mode and gain and sets the HP mode. This register is reset at POR. Bit Bit Name Default Access 7 OP_REG_ON 0 R/W Defines which register is used for the opamp and HP settings. 0: settings of register 33h and 34h are used 1: register 0B and 0Ch are used 6 HP_MODE 0 R/W Selects the line input mode 0: single ended stereo mode 1: mono differential mode 5:2 OP2R 0000 R/W Mode and volume settings for right OP2, adjustable in 15 steps of 0.75dB 0000: OP2R in inverting mode 0001: 0 dB gain, OP2R in non inverting mode 0001: 0.75 dB gain, non inverting .., 1110: 9.75dB gain, non inverting 1111:.10.5 dB gain, non inverting 1 OP2R_ON 0 R/W Enables right OP 2 0: right OP2 is switched off 1: right OP2 is enabled 0 OP1R_ON 0 R/W Enables right OP 1 0: right OP1 is switched off 1: right OP1 is enabled www.austriamicrosystems.com Bit Description Revision 0.90 32 - 61 AS3421 AS3422 Datasheet - R e g i s t e r D e s c r i p t i o n Table 21. SYSTEM Register Name Base Default SYSTEM 2-wire serial 31h SYSTEM Register Offset: 20h This register is reset at a POR. Bit Bit Name Default Access Bit Description 7:4 Design_Version 1001 R 3 TESTREG_ON 0 R/W 0: normal operation 1: enables writing to test register 3Eh & 3Fh to configure the OTP and set the access mode. 2 MONITOR_ON 0 R/W Enables the monitor mode 0: normal operation 1: monitor mode enabled 1 CONT_PWRUP 0 R/W Continues the automatic power-up sequence when using the I2C mode 0: chip stops the power-up sequence after the supplies are stable, switching on individual blocks has to be done via I2C commands 1: automatic power-up sequence is continued 0 PWR_HOLD 1 R/W 0: power up hold is cleared and AFE will power down 1: is automatically set to on after power on AFE number to identify the design version 1001: for chip version 1v1 Table 22. PWR_SET Register Name PWR_SET Base Default 2-wire serial 0x11 1111b (stand alone mode) 0x00 0000b (I2C mode) Power Setting Register Offset: 21h Please be aware that writing to this register will enable/disable the corresponding blocks, while reading gets the actual status. It is not possible to read back e.g ILED settings. This register is reset at POR. Bit Bit Name Default Access 7 PWR_REG_ON 0 R/W 6 LOW_BAT x R VBAT supervisor status 0: VBAT is above brown out level 1: BVDD has reached brown out level 5 PWRUP_COMPLETE x R Power-Up sequencer status 0: power-up sequence incomplete 1: power-up sequence completed 4 HP_ON 0 W 0: switches HP stage off 1: switches HP stage on x R 0: HP stage not powered 1: normal operation 0 W 0: switches microphone stage off 1: switches microphone stage on x R 0: microphone stage not powered 1: normal operation 3 MIC_ON www.austriamicrosystems.com Bit Description Defines which register is used for the power settings. 0: all blocks stay on as defined in the start-up sequence 1: register 21h is used Revision 0.90 33 - 61 AS3421 AS3422 Datasheet - R e g i s t e r D e s c r i p t i o n Table 22. PWR_SET Register Name Base Default PWR_SET 2-wire serial 0x11 1111b (stand alone mode) 0x00 0000b (I2C mode) Power Setting Register Offset: 21h Please be aware that writing to this register will enable/disable the corresponding blocks, while reading gets the actual status. It is not possible to read back e.g ILED settings. This register is reset at POR. Bit Bit Name Default Access 2 LIN_ON 0 W 0: switches line input stage off 1: switches line input stage on x R 0: line input stage not powered 1: normal operation 0 W 0: switches microphone supply charge pump off 1: switches microphone supply charge pump on x R 0: microphone supply charge pump not powered 1: normal operation 0 W 0: switches microphone supply off 1: switches microphone supply on x R 0: microphone supply not enabled 1: normal operation 1 0 MICS_CP_ON MICS_ON www.austriamicrosystems.com Bit Description Revision 0.90 34 - 61 AS3421 AS3422 Datasheet - R e g i s t e r D e s c r i p t i o n Table 23. ANC_L2 Register Name ANC_L2 Base Default 2-wire serial 80h (OTP) Left OTP Microphone Input Register (2nd OTP option) Offset: 10h Bit Configures the gain for the left microphone input. This is a special register, writing needs to be enabled by writing 10b to Reg 3Fh first. This register is reset at POR and gets loaded with the OTP fuse contents. Bit Name Default Access 7 TEST_BIT_5 1 R 6:0 MICL_VOL_OTP2 000 0000 R/W Bit Description for testing purpose only Volume settings for left microphone input, adjustable in 127 steps of 0.375dB 00 0000: MUTE 00 0001: -11.25dB gain 00 0010: -10.875 dB gain .. 11 1110: 35.625dB gain 11 1111: 36 dB gain Table 24. ANC_R2 Register Name Base Default ANC_R2 2-wire serial 00h (OTP) Right OTP Microphone Input Register (2nd OTP option) Offset: 11h Configures the gain for the left microphone input. This is a special register, writing needs to be enabled by writing 10b to Reg 3Fh first. This register is reset at POR and gets loaded with the OTP fuse contents. Bit Bit Name Default Access 7 ALT1_LOCK 0 R/W 0: additional bits can be fused inside register 10h & 11h 1: OTP fusing for register 10h & 11h gets locked, no more changes can be done. 6:0 MICR_VOL_OTP2 000 0000 R/W Volume settings for right microphone input, adjustable in 127 steps of 0.375dB 00 0000: MUTE 00 0001: -11.25dB gain 00 0010: -10.875 dB gain .. 11 1110: 35.625dB gain 11 1111: 36 dB gain www.austriamicrosystems.com Bit Description Revision 0.90 35 - 61 AS3421 AS3422 Datasheet - R e g i s t e r D e s c r i p t i o n Table 25. ANC_L3 Register Name ANC_L3 Base Default 2-wire serial 80h (OTP) Left OTP Microphone Input Register (3rd OTP option) Offset: 12h Bit Configures the gain for the left microphone input. This is a special register, writing needs to be enabled by writing 10b to Reg 3Fh first. This register is reset at POR and gets loaded with the OTP fuse contents. Bit Name Default Access 7 TEST_BIT_6 1 R 6:0 MICL_VOL_OTP3 000 0000 R/W Bit Description for testing purpose only Volume settings for left microphone input, adjustable in 127 steps of 0.375dB 00 0000: MUTE 00 0001: -11.25dB gain 00 0010: -10.875 dB gain .. 11 1110: 35.625dB gain 11 1111: 36 dB gain Table 26. ANC_R3 Register Name Base Default ANC_R3 2-wire serial 00h (OTP) Right OTP Microphone Input Register (3rd OTP option) Offset: 13h Configures the gain for the left microphone input. This is a special register, writing needs to be enabled by writing 10b to Reg 3Fh first. This register is reset at POR and gets loaded with the OTP fuse contents. Bit Bit Name Default Access Bit Description 7 ALT2_LOCK 0 R/W 0: additional bits can be fused inside register 12h & 13h 1: OTP fusing for register 12h & 13h gets locked, no more changes can be done. 6:0 MICR_VOL_OTP3 000 0000 R/W Volume settings for right microphone input, adjustable in 127 steps of 0.375dB 00 0000: MUTE 00 0001: -11.25dB gain 00 0010: -10.875 dB gain .. 11 1110: 35.625dB gain 11 1111: 36 dB gain www.austriamicrosystems.com Revision 0.90 36 - 61 AS3421 AS3422 Datasheet - R e g i s t e r D e s c r i p t i o n Table 27. ANC_L4 Register Name ANC_L4 Base Default 2-wire serial 80h (OTP) Left OTP Microphone Input Register (4th OTP option) Offset: 14h Bit Configures the gain for the left microphone input. This is a special register, writing needs to be enabled by writing 10b to Reg 3Fh first. This register is reset at POR and gets loaded with the OTP fuse contents. Bit Name Default Access 7 TEST_BIT_7 1 R 6:0 MICL_VOL_OTP4 000 0000 R/W Bit Description for testing purpose only Volume settings for left microphone input, adjustable in 127 steps of 0.375dB 00 0000: MUTE 00 0001: -11.25dB gain 00 0010: -10.875 dB gain .. 11 1110: 35.625dB gain 11 1111: 36 dB gain Table 28. ANC_R4 Register Name ANC_R4 Base Default 2-wire serial 00h (OTP) Right OTP Microphone Input Register (4th OTP option) Offset: 15h Configures the gain for the left microphone input. This is a special register, writing needs to be enabled by writing 10b to Reg 3Fh first. This register is reset at POR and gets loaded with the OTP fuse contents. Bit Bit Name Default Access 7 ALT3_LOCK 0 R/W 0: additional bits can be fused inside register 14h & 15h 1: OTP fusing for register 14h & 15h gets locked, no more changes can be done. 6:0 MICR_VOL_OTP4 000 0000 R/W Volume settings for right microphone input, adjustable in 127 steps of 0.375dB 00 0000: MUTE 00 0001: -11.25dB gain 00 0010: -10.875 dB gain .. 11 1110: 35.625dB gain 11 1111: 36 dB gain www.austriamicrosystems.com Bit Description Revision 0.90 37 - 61 AS3421 AS3422 Datasheet - R e g i s t e r D e s c r i p t i o n Table 29. MICS_CNTR Register Name Base Default MICS_CNTR 2-wire serial 00h (OTP) Microphone Supply Regsiter Offset: 16h Configures the low battery threshold value Bit Bit Name Default Access Bit Description 3 LowBat 0 R/W 0: default LowBat value 1: 100mV increase of LowBat threshold 0 DEL_ ANC_MUX 0 R/W 0: default startup timing of AS3421/22 1: HP_MUX_OTP is set to OTP value 0.8s after device startup Table 30. PWRUP_CNTR Register Name Base Default PWRUP_CNTR 2-wire serial 00h (OTP) PowerUp Control Register Offset: 17h Configures chip start-up speed. This is a special register, writing needs to be enabled by writing 10b to Reg 3Fh first. This register is reset at POR and gets loaded with the OTP fuse contents. Bit Bit Name Default Access Bit Description 7 SEQ_LOCK 0 R/W 0: additional bits can be fused inside register 16h & 17h 1: OTP fusing for register 16h & 17h gets locked, no more changes can be done. 6:2 FAST_START 0 0000 R/W 0h: ~900ms start-up time 0Eh: ~600ms start-up time 1 LIN_AGC_OFF 0 R/W 0: Line Input AGC enabled 1: Line Input AGC switched off 0 MIC_AGC_OFF 0 R/W 0:Microphone Input AGC enabled 1: Microphone Input AGC switched off Table 31. ANC_L Register Name Base Default ANC_L 2-wire serial 80h (OTP) Left OTP Microphone Input Register Offset: 30h Configures the gain for the left microphone input. This is a special register, writing needs to be enabled by writing 10b to Reg 3Fh first. This register is reset at POR and gets loaded with the OTP fuse contents. Bit Bit Name Default Access 7 TEST_BIT_1 1 R 6:0 MICL_VOL_OTP 000 0000 R/W www.austriamicrosystems.com Bit Description for testing purpose only Volume settings for left microphone input, adjustable in 127 steps of 0.375dB 00 0000: MUTE 00 0001: -11.25dB gain 00 0010: -10.875 dB gain .. 11 1110: 35.625dB gain 11 1111: 36 dB gain Revision 0.90 38 - 61 AS3421 AS3422 Datasheet - R e g i s t e r D e s c r i p t i o n Table 32. ANC_R Register Name Base Default ANC_R 2-wire serial 80h (OTP) Right OTP Microphone Input Register Offset: 31h Bit Bit Name Configures the gain for the left microphone input. This is a special register, writing needs to be enabled by writing 10b to Reg 3Fh first. This register is reset at POR and gets loaded with the OTP fuse contents. Default Access 7 TEST_BIT_2 1 R 6:0 MICR_VOL_OTP 000 0000 R/W www.austriamicrosystems.com Bit Description for testing purpose only Volume settings for right microphone input, adjustable in 127 steps of 0.375dB 00 0000: MUTE 00 0001: -11.25dB gain 00 0010: -10.875 dB gain .. 11 1110: 35.625dB gain 11 1111: 36 dB gain Revision 0.90 39 - 61 AS3421 AS3422 Datasheet - R e g i s t e r D e s c r i p t i o n Table 33. MIC_MON Register Name MIC_MON Base Default 2-wire serial 00h (OTP) OPT Microphone Monitor Mode Register Configures the gain for the microphone input in monitor mode. This is a special register, writing needs to be enabled by writing 10b to Reg 3Fh first. This register is reset at POR and gets loaded with the OTP fuse contents. Offset: 32h Bit Bit Name Default Access Bit Description 7 MON_MODE 0 R/W 0: monitor mode is working with fixed microphone gain 1: monitor mode uses adjustable gain via the VOL pin 6:0 MIC_MON_OTP 000 0000 R/W Volume settings for microphone input during monitor mode, adjustable in 127 steps of 0.375dB. If MON_MODE bit is set to 1 the gain can be further adjusted via the VOL pin. 00 0000: MUTE 00 0001: -11.25dB gain 00 0010: -10.875 dB gain .. 11 1110: 35.625dB gain 11 1111: 36 dB gain Table 34. AUDIO_SET Register Name Base Default AUDIO_SET 2-wire serial 00h (OTP) OPT Audio Setting Register Offset: 33h Configures the audio settings. This is a special register, writing needs to be enabled by writing 10b to Reg 3Fh first. This register is reset at POR and gets loaded with the OTP fuse contents. Bit Bit Name Default Access Bit Description 7 NO_PB_MODE 0 R/W This bit defines if the low power music playback mode is enabled or not. In case the bit is set to ‘0’, music playback mode can be entered by pulling the ANC_CSDA pin low. In case the bit is set to ‘1’ the music playback mode is disabled. Pulling the ANC_CSDA pin low has no influence. 0: Music playback mode enabled 1: Music playback mode disabled 6 VOL_BUTTON_MODE 0 R/W If bit is set to ‘1’ the ANC_CSDA pin allows the user to control the line input gain via push-buttons. If bit is set to ‘0’, the volume control is disabled. Please mind that if VOL_BUTTON_MODE bit is set to ‘1’ entering music playback mode via ANC_CSDA pin is not possible any more. 0: Volume mode via push-button disabled 1: Volume mode via push-button enabled 5 LINE_GAIN_+3dB_OTP 0 R/W Selects the line input operating gain range. If this bit is set the gain range of the line input amplifiers is shifted by +3dB. 0: Line Input gain range from -46.5dB...0dB 1: Line Input gain range from -43.5dB...+3dB 4 MIC_MODE_OTP 0 R/W 0: microphone input stage operating in single ended mode 1: normal operating in mono balanced www.austriamicrosystems.com Revision 0.90 40 - 61 AS3421 AS3422 Datasheet - R e g i s t e r D e s c r i p t i o n Table 34. AUDIO_SET Register Name Base Default AUDIO_SET 2-wire serial 00h (OTP) OPT Audio Setting Register Offset: 33h Configures the audio settings. This is a special register, writing needs to be enabled by writing 10b to Reg 3Fh first. This register is reset at POR and gets loaded with the OTP fuse contents. Bit Bit Name Default Access 3 HP_MODE_OTP 0 R/W 0: headphone stage operating in single ended mode 1: normal operating in mono balanced 2:0 LIN_MON_ATTEN 000 R/W Volume settings for line input during monitor mode, adjustable in 7 steps of 6dB and mute. 000: 0dB gain 001: -6dB gain .. 110: -36dB gain 111: MUTE www.austriamicrosystems.com Bit Description Revision 0.90 41 - 61 AS3421 AS3422 Datasheet - R e g i s t e r D e s c r i p t i o n Table 35. GP_OP Register Name GP_OP Base Default 2-wire serial 00h (OTP) OTP General Purpose Operational Amplifier Register Enables the opamp stages, defines opamp 2 mode and gain and sets the HP input multiplexer. This is a special register, writing needs to be enabled by writing 10b to Reg 3Fh first. This register is reset at POR and gets loaded with the OTP fuse contents. Offset: 34h Bit Bit Name Default Access Bit Description 7:6 HP_MUX_OTP 00 R/W Multiplexes the analog audio signal to HP amp 00: MIC: selects QMICL/R output 01:OP1: selects QOP1L/R outputs 10:OP2: selects QOP2L/R output 11: open: no signal mixed together with the line input signal 5:2 OP2_OTP 0000 R/W Mode and volume settings for OP2, adjustable in 15 steps of 0.75dB 0000: OP2L in inverting mode 0001: 0 dB gain, OP2L in non inverting mode 0001: 0.75 dB gain, non inverting .., 1110: 9.75dB gain, non inverting 1111:.10.5 dB gain, non inverting 1 OP2_ON 0 R/W 0: OP2 is switched off 1: left OP2 is enabled 0 OPL_ON 0 R/W 0: OP1 is switched off 1: OP1 is enabled Table 36. OTP_SYS Register Name Base Default OTP_SYS 2-wire serial 40h (OTP) OTP System Settings Register Offset: 35h Defines several system settings for OTP operation. This is a special register, writing needs to be enabled by writing 10b to Reg 3Fh first. This register is reset at POR and gets loaded with the OTP fuse contents. Bit Bit Name Default Access 7 MAIN_LOCK 0 R/W 6 TEST_BIT_3 1 R 5:4 MON_HP_MUX 00 R/W Multiplexes the analog audio signal to HP amp in monitor mode 00: MIC: selects QMICL/R output 01: OP1: selects QOP1L/R outputs 10:OP2: selects QOP2L/R output 11: open: no signal mixed together with the line input signal 2 CP_MODE_OTP 0 R/W This bit controls the operating mode of the microphone supply charge pump. 0: Standard low noise operation 1: Increased output voltage 1 MICS_CP_OFF 0 R/W 0: MICS charge pump is enabled 1: MICS charge pump is switched off 0 I2C 0 R/W 0: I2C and stand alone mode start-up possible 1: chip starts-up in I2C mode only www.austriamicrosystems.com Bit Description 0: additional bits can be fused inside the OTP 1: OTP fusing gets locked, no more changes can be done for testing purpose only Revision 0.90 42 - 61 AS3421 AS3422 Datasheet - R e g i s t e r D e s c r i p t i o n Table 37. CONFIG_1 Register Name Base Default CONFIG_1 2-wire serial 00h OTP Configuration Register Offset: 3Eh Bit Controls the clock configuration. This is a special register, writing needs to be enabled by writing 9h to Reg 20h first. This register is reset at POR and gets loaded with the OTP fuse contents. Bit Name Default Access 7:4 - 0000 n/a 3 EXTBURNCLK 0 n/a 2:0 - 000 n/a Bit Description 0: ext. clock for OTP burning disabled 1: ext. clock for OTP burning enabled Table 38. CONFIG_2 Register Name Base Default CONFIG_2 2-wire serial 00h OTP Access Configuration Register Offset: 3Fh Bit Controls the OTP access. This is a special register, writing needs to be enabled by writing 9h to Reg 20h first. This register is reset at POR and gets loaded with the OTP fuse contents. Bit Name Default 7:6 - 000 n/a 5 TM34 0 n/a This Register defines the Register bank selection for Register TM_REG34-35 and TMREG30-33. Depending on TM34 you can select either between Register bank 14h-17h and 10h-13h enabled or 30h-33h and 34h-37h enabled. 0: test mode Registers 14h-17h and 10h-13h disabled test mode Registers 30h-33h and 34h-37h enabled 1: test mode Registers 14h-17h and 10h-13h enabled test mode Registers 30h-33h and 34h-37h disabled 4 BURNSW 0 n/a 0: BURN switch from LINL to VNEG is disabled 1: BURN switch from LINL to VNEG is enabled 3 TM_REG34-35 0 n/a 0: test mode for Register 34h-35h disabled test mode for Register 14h-17h disabled 1: test mode for Register 34h-35h enabled test mode for Register 14h-17h enabled 2 TM_REG30-33 0 n/a 0: test mode for Register 30h-33h disabled test mode for Register 10h-13h disabled 1: test mode for Register 30h-33h enabled test mode for Register 10h-13h enabled 1:0 OTP_MODE 00 R/W Controls the OTP access 00: READ 01: LOAD 10: WRITE 11: BURN www.austriamicrosystems.com Access Bit Description Revision 0.90 43 - 61 AS3421 AS3422 Datasheet - A p p l i c a t i o n I n f o r m a t i o n 11 Application Information 11.1 AS3422 Feedback Application Examples Figure 35. AS3422 Feedback Application Example with Bluetooth I2C Control www.austriamicrosystems.com Revision 0.90 44 - 61 AS3421 AS3422 Datasheet - A p p l i c a t i o n I n f o r m a t i o n Figure 36. AS3422 Feedback Application Example with Bluetooth ROM Version (No I2C Control) www.austriamicrosystems.com Revision 0.90 45 - 61 D C B 1 2 220nF 220nF 220nF 220nF C7 C8 C9 C10 R4 10k R3 10k Vanc AGND GND 100n C1 Vneg RC Filter Networks to be developed individually for each headset. C3 AS3422 QOP1R AGND IOP2R QOP2R VSS HPL HPVSS HPR HPVDD AGND GND SET OUT 6 4 5 Vanc GND 10u GND Vneg RC Filter Networks to be developed individually for each headset. 17 18 19 20 21 22 23 24 47k R8 R7 4 T-a1 4 15k AGND AGND 100n C6 GND GND C5 a low noise supply Vanc should be AS1363-AD EN POK IN U2 Right ANC Microphone 2k2 MICS 3 2 1 GND U1 AS3422 R6 GND 1u ANC POWER GND 1uF C15 2k2 3 10u C2 Vdcdc R5 MICS MICS LINR_N LINR_P LINL_P LINL_N AGND QMICL QLINL IOP1L Left ANC Microphone 8 7 6 5 4 3 2 1 Vneg 31 A CAUTION: Exposed pad must be connect to VNEG or left unconnected. Exposed pad must NOT be connected to GND or AGND! 3 26 2 33 VNEG 32 QOP1L CSDA 9 30 MICL 4.7uF C12 IOP2L 29 MICS 12 CSCL 10 QOP2L 28 CPN MICR 13 4.7uF 10uF C13 Revision 0.90 C14 11 VNEG 27 GND QMICR 14 25 VBAT IOP1R CPP QLINR 15 www.austriamicrosystems.com 16 1 Speaker Left Speaker Right D C B A AS3421 AS3422 Datasheet - A p p l i c a t i o n I n f o r m a t i o n Figure 37. AS3422 Schematic - Stereo Bluetooth Feedback Application with I2C Control 46 - 61 D C B A 1 2 220nF 220nF 220nF C8 C9 C10 GND 10k 10k S1 ANC ON/OFF R4 Vanc AGND R3 Vanc 220nF C7 T2 CAUTION: Exposed pad must be connect to VNEG or left unconnected. Exposed pad must NOT be connected to GND or AGND! 1 GND 100n C1 Vneg RC Filter Networks to be developed individually for each headset. MICS LINR_N LINR_P LINL_P LINL_N AGND QMICL QLINL IOP1L 2k2 AGND Left ANC Microphone T1 Testpoint CSCL R5 MICS Testpoint CSCL 8 7 6 5 4 3 2 1 Vneg 3 31 T3 Testpoint VNEG 3 10u C2 C3 AS3422 GND 1u AGND GND SET OUT 4 5 6 GND 10u GND Vneg RC Filter Networks to be developed individually for each headset. 17 18 19 20 21 22 23 24 47k R8 R7 4 T-a1 4 15k AGND AGND 100n C6 GND GND Vanc C5 a low noise supply Vanc should be AS1363-AD EN POK I IN U2 Right ANC Microphone 2k2 QOP1R IOP2R QOP2R VSS HPL HPVSS HPR HPVDD R6 MICS 3 2 1 GND U1 AS3422 GND 1uF C15 ANC POWER Vdcdc 26 2 1 2 1 1 33 VNEG 32 9 MICL QOP1L CSDA IOP2L CSCL 10 30 QOP2L 29 VNEG MICS 4.7uF C12 12 10uF C13 11 28 CPN MICR 13 4.7uF Revision 0.90 C14 25 VBAT IOP1R 27 GND QMICR 14 CPP QLINR 15 www.austriamicrosystems.com 16 1 Speaker Left Speaker Right D C B A AS3421 AS3422 Datasheet - A p p l i c a t i o n I n f o r m a t i o n Figure 38. AS3422 Schematic - Stereo Bluetooth Feedback Application with ROM Version (No I2C Control) 47 - 61 AS3421 AS3422 Datasheet - A p p l i c a t i o n I n f o r m a t i o n 11.2 AS3421 Feed Forward Application Examples Figure 39. AS3421 Feed-Forward Application Example with Bluetooth I2C Control www.austriamicrosystems.com Revision 0.90 48 - 61 AS3421 AS3422 Datasheet - A p p l i c a t i o n I n f o r m a t i o n Figure 40. AS3421 Feed-Forward Application Example with Bluetooth ROM Version (No I2C Control) www.austriamicrosystems.com Revision 0.90 49 - 61 D C B A 1 2 220nF C9 220nF 220nF C8 C10 220nF C7 R4 10k R3 10k Vanc AGND 10u C2 3 6 5 4 3 2 1 Vneg RC Filter Networks to be developed individually for each headset. GND 100n C1 AGND 3 2k2 R5 MICS LINR_N LINR_P LINL_P LINL_N AGND QMICL Left ANC Microphone Vneg CAUTION: Exposed pad must be connect to VNEG or left unconnected. Exposed pad must NOT be connected to GND or AGND! 2 25 EX_PAD 24 IOP1L ANC_CSDA 7 23 C3 AS3421 QOP1L 22 VNEG MICL GND 4.7uF C12 9 MICS 10 10µF MODE_CSCL 8 21 CPN 20 GND 1u GND 1uF C15 AGND GND SET OUT GND GND 100n 4 C6 AGND T-a1 AGND Speaker Left Speaker Right 15k GND a low noise supply C5 GND 47k R8 R7 Vanc should be 4 5 6 4 10u Vanc AS1363-AD EN POK IN U2 RC Filter Networks to be developed individually for each headset. 13 14 15 16 17 18 U1 AS3421 3 2 1 Right ANC Microphone 2k2 R6 MICS MICS IOP1R QOP1R HPL HPR HPVDD VBAT GND ANC POWER Vdcdc 19 CPP QMICR 12 MICR 11 C13 Revision 0.90 4.7uF www.austriamicrosystems.com C14 1 D C B A AS3421 AS3422 Datasheet - A p p l i c a t i o n I n f o r m a t i o n Figure 41. AS3421 Schematic - Stereo Feed-Forward Bluetooth Application with I2C Control 50 - 61 D C B A T3 Testpoint VNEG 1 1 2 220nF 220nF 220nF C8 C9 C10 GND 10k 10k S1 ANC ON/OFF R4 Vanc T2 AGND R3 Vanc 220nF C7 Vneg 6 5 4 3 2 1 Vneg 3 AGND 2k2 R5 MICS LINR_N LINR_P LINL_P LINL_N AGND QMICL Left ANC Microphone T1 Testpoint CSCL 10u C2 3 RC Filter Networks to be developed individually for each headset. GND 100n C1 Testpoint CSCL CAUTION: Exposed pad must be connect to VNEG or left unconnected. Exposed pad must NOT be connected to GND or AGND! 2 1 2 1 1 25 EX_PAD 24 IOP1L ANC_CSDA 7 23 C3 AS3421 QOP1L 22 VNEG MICL GND 4.7uF C12 9 MICS 10 10µF MODE_CSCL 8 21 CPN 20 GND 1u Vdcdc GND 1uF C15 AGND GND SET OUT GND GND 100n 4 C6 AGND T-a1 AGND Speaker Left Speaker Right 15k GND a low noise supply C5 GND 47k R8 R7 Vanc should be 4 5 6 4 10u Vanc AS1363-AD EN POK I IN U2 RC Filter Networks to be developed individually for each headset. 13 14 15 16 17 18 U1 AS3421 3 2 1 Right ANC Microphone 2k2 R6 MICS MICS IOP1R QOP1R HPL HPR HPVDD VBAT GND ANC POWER 19 CPP QMICR 12 MICR 11 C13 Revision 0.90 4.7uF www.austriamicrosystems.com C14 1 D C B A AS3421 AS3422 Datasheet - A p p l i c a t i o n I n f o r m a t i o n Figure 42. AS3421 Schematic - Stereo Feed-Forward Bluetooth Application ROM Version (No I2C Control) 51 - 61 AS3421 AS3422 Datasheet - A p p l i c a t i o n I n f o r m a t i o n 11.3 Layout Recommendation Whereever you have audio circuits mixed with power management layout of the blocks is a critical issue. The AS3421/22 has an integrated charge pump which operates at a frequency of 1Mhz. If the layout of the PCB is not done properly the charge pump can directly influence the audio performance of the device. Therefore it is very important to make sure that the layout of the charge pump is done properly. The layout recommendation shown in Figure 43 below shows an example placement of the components of the charge pump. The reference designators of the components used in the example refer to the schematic shown in Figure 37. It can be seen clearly that the ground pins of all capacitors as well as the ground pin of AS3422 are placed closely. This compact placement of the components help to minimize high frequency cross over currents all over the PCB and therefore helps to improve the audio quality. A dedicated ground plane on the top (red) layer minimizes the resistance between the ground pads of the components. The ground plane (GND) is then connected to the analog ground (AGND) at a single point which is indicated with three vias in the example. Figure 43. AS3422 CP Layout Recommendation For component references please refer to figure 24. IA connection to analog round plane (AGND) If the physical alignment of the components allows it, it is also recommended to connect the charge pump ground plane on top layer directly to the battery ground terminal of your device. The analogue- (AGND) and charge pump ground plane (GND) are then connected together directly at the battery terminal. This concept is also know as star shaped ground concept shown in Figure 44 below. Figure 44. AS3422 Star Shaped Ground Concept For component references please refer to figure 24. Charge pump ground (GND) and analog ground (AGND) are directly connected together at negative battery terminal. www.austriamicrosystems.com Revision 0.90 52 - 61 AS3421 AS3422 Datasheet - A p p l i c a t i o n I n f o r m a t i o n The layout examples showed in the examples before are based on AS3422. The AS3421 has of course a smaller package than AS3422, therefore the alignment of the charge pump components is different. A layout recommendation for AS3421 is shown in Figure 45 below. Figure 45. AS3421 CP Layout Recommendation For component references please refer to figure 26. VIA connection to analog round plane (AGND) 11.4 Bill of Materials The following section shows the Bill of Materials which is necessary to operate the device. The necessary R-C filter networks which are necessary for gain- and phase compensation are excluded. These components very much depend on the acoustic design of each headset. Both devices basically need 17 external component for standard operation without the necessary filter components. The reference designator of the components shown in Table 39 refer to the schematics shown in Figure 37 and Figure 41. Table 39. AS3421/22 Bill of Materials POS 1 2 3 4 5 6 7 8 9 10 11 12 Sum Reference U1 U2 C3, C15 C1, C6 C7, C8, C9, C10 C13 C12, C14 R5, R6 C2, C5 R7 R8 R3, R4 Value/Name AS3421 AS1363-AD 1µF 100nF 220nF 10µF 4.7uF 2k2 10µF 15k 47k 10k www.austriamicrosystems.com Description Stereo Bluetooth ANC headphone driver circuit Low Drop Voltage Regulator Charge Pump flying capacitor; +/- 10% tolerance and LDO support PMU Blocking capacitors; +/- 10% tolerance Audio DC coupling capacitors; +/- 10% tolerance Microphone supply filter capacitor; +/- 10% tolerance Microphone DC coupling capacitors; +/-5% tolerance Microphone bias resistors; +/- 5%tolerance PMU Blocking capacitors; +/- 10% tolerance Voltage Regulator feedback resistor Voltage Regulator feedback resistor Two wire interface pull up resistors; +/- 10% tolerance Revision 0.90 Count 1 1 2 2 4 1 2 2 2 1 1 2 21 53 - 61 AS3421 AS3422 Datasheet - A p p l i c a t i o n I n f o r m a t i o n 11.5 PCB Footprint Recommendation CAUTION: Please mind that the recommendations are designed according to IPC-7351B standard. The footprints might need little changes in order to achieve best reliability in production! Figure 46. AS3421 PCB Footprint Recommendation www.austriamicrosystems.com Pin 1 RECOMMENDED LAND PATTERN OW COMPONENT DENSITY TOP VIEW Silk Screen Pin 1 RECOMMENDED LAND PATTERN MEDIUM COMPONENT DENSITY TOP VIEW Silk Screen Pin 1 RECOMMENDED LAND PATTERN HIGH COMPONENT DENSITY TOP VIEW Silk Screen Revision 0.90 54 - 61 AS3421 AS3422 Datasheet - A p p l i c a t i o n I n f o r m a t i o n Figure 47. AS3422 PCB Footprint Recommendation CAUTION: Please mind that the recommendations are designed according to IPC-7351B standard. The footprints might need little changes in order to achieve best reliability in production! Pin 1 www.austriamicrosystems.com RECOMMENDED LAND PATTERN OW COMPONENT DENSITY TOP VIEW Silk Screen Pin 1 RECOMMENDED LAND PATTERN MEDIUM COMPONENT DENSITY TOP VIEW Silk Screen Pin 1 RECOMMENDED LAND PATTERN HIGH COMPONENT DENSITY TOP VIEW Silk Screen Revision 0.90 55 - 61 AS3421 AS3422 Datasheet - P a c k a g e D r a w i n g s a n d M a r k i n g 12 Package Drawings and Marking Figure 48. QFN Marking Table 40. Package Code YYWWIZZ YY WW X ZZ last two digits of the year manufacturing week plant identifier free choice / traceability code www.austriamicrosystems.com Revision 0.90 56 - 61 AS3421 AS3422 Datasheet - P a c k a g e D r a w i n g s a n d M a r k i n g Figure 49. AS3421, 24-pin QFN 0.5mm Pitch www.austriamicrosystems.com Revision 0.90 57 - 61 AS3421 AS3422 Datasheet - P a c k a g e D r a w i n g s a n d M a r k i n g Figure 50. AS2322 32-pin QFN 0.5mm Pitch www.austriamicrosystems.com Revision 0.90 58 - 61 AS3421 AS3422 Datasheet - R e v i s i o n H i s t o r y Revision History Revision Date Owner Description 0.2 25.1.2012 hgt initial release 0.3 14.3.2012 hgt updated low power playback mode and pin descriptions 0.4 11.6.2012 hgt updated microphone parameters Note: Typos may not be explicitly mentioned under revision history. www.austriamicrosystems.com Revision 0.90 59 - 61 AS3421 AS3422 Datasheet - O r d e r i n g I n f o r m a t i o n 13 Ordering Information The devices are available as the standard products shown in Table 41. Table 41. Ordering Information Ordering Code Description Delivery Form Package AS3421-EQFP Low Power Ambient Noise-Cancelling Speaker Driver Tape & Reel dry pack QFN 24 [4.0x4.0x0.85mm] 0.5mm pitch AS3421-EQFP-500 Low Power Ambient Noise-Cancelling Speaker Driver Tape & Reel dry pack QFN 24 [4.0x4.0x0.85mm] 0.5mm pitch AS3422-EQFP Low Power Ambient Noise-Cancelling Speaker Driver Tape & Reel dry pack QFN 32 [5.0x5.0x0.85mm] 0.5mm pitch AS3422-EQFP-500 Low Power Ambient Noise-Cancelling Speaker Driver Tape & Reel dry pack QFN 32 [5.0x5.0x0.85mm] 0.5mm pitch Note: All products are RoHS compliant and austriamicrosystems green. Buy our products or get free samples online at ICdirect: http://www.austriamicrosystems.com/ICdirect For further information and requests, please contact us mailto:sales@austriamicrosystems.com or find your local distributor at http://www.austriamicrosystems.com/distributor www.austriamicrosystems.com Revision 0.90 60 - 61 AS3421 AS3422 Datasheet - C o p y r i g h t s Copyrights Copyright © 1997-2012, austriamicrosystems AG, Tobelbaderstrasse 30, 8141 Unterpremstaetten, Austria-Europe. Trademarks Registered ®. All rights reserved. The material herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. All products and companies mentioned are trademarks or registered trademarks of their respective companies. Disclaimer Devices sold by austriamicrosystems AG are covered by the warranty and patent indemnification provisions appearing in its Term of Sale. austriamicrosystems AG makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. austriamicrosystems AG reserves the right to change specifications and prices at any time and without notice. Therefore, prior to designing this product into a system, it is necessary to check with austriamicrosystems AG for current information. This product is intended for use in normal commercial applications. Applications requiring extended temperature range, unusual environmental requirements, or high reliability applications, such as military, medical life-support or life-sustaining equipment are specifically not recommended without additional processing by austriamicrosystems AG for each application. For shipments of less than 100 parts the manufacturing flow might show deviations from the standard production flow, such as test flow or test location. The information furnished here by austriamicrosystems AG is believed to be correct and accurate. However, austriamicrosystems AG shall not be liable to recipient or any third party for any damages, including but not limited to personal injury, property damage, loss of profits, loss of use, interruption of business or indirect, special, incidental or consequential damages, of any kind, in connection with or arising out of the furnishing, performance or use of the technical data herein. No obligation or liability to recipient or any third party shall arise or flow out of austriamicrosystems AG rendering of technical or other services. Contact Information Headquarters austriamicrosystems AG Tobelbaderstrasse 30 A-8141 Unterpremstaetten, Austria Tel: +43 (0) 3136 500 0 Fax: +43 (0) 3136 525 01 For Sales Offices, Distributors and Representatives, please visit: http://www.austriamicrosystems.com/contact www.austriamicrosystems.com Revision 0.90 61 - 61